Introducing EDA Prompt Generator: Domain-Specific Prompts for Chip Design & Verification
As a chip verification engineer, I ask LLMs for help constantly — draft a UVM sequence, explain a CDC violation, sanity-check an SDC constraint, summarize a synthesis timing report. The problem is that general-purpose chatbots have no idea what a good EDA prompt looks like. Every time, I was manually writing the same scaffolding: who the model should act as, what technical context it needs, what the actual task is, what constraints apply, and what shape the output should take. Redoing that by hand for every question gets old fast. So I built EDA Prompt Generator to automate that scaffolding — you type a short EDA requirement, it hands back a structured, professional prompt ready to paste into whatever model you’re using. ...